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low power, 16-/24-bit sigma-delta adc ad7788/ad7789 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features ad7788: 16-bit resolution ad7789: 24-bit resolution power supply: 2.5 v to 5.25 v operation normal: 75 a maximum power-down: 1 a maximum rms noise: 1.5 v ad7788: 16-bit p-p resolution ad7789: 19-bit p-p resolution (21.5 bits effective) integral nonlinearity: 3.5 ppm typical simultaneous 50 hz and 60 hz rejection internal clock oscillator v dd monitor channel 10-lead msop interface 3-wire serial spi?, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications smart transmitters battery applications portable instrumentation sensor measurement temperature measurement pressure measurement weigh scales 4 to 20 ma loops functional block diagram 03539-0-001 serial interface and control logic clock *ad7788: 16-bit adc ad7789: 24-bit adc ain(+) ain(?) gnd - ? adc* ad7788/ ad7789 refin(+) refin( ? ) v dd dout/rdy din sclk cs figure 1. general description the ad7788/ad7789 are low power, low noise, analog front ends for low frequency measurement applications. the ad7789 contains a low noise 24-bit -? adc with one differential input. the ad7788 is a 16-bit version of the ad7789. the device operates from an internal clock. therefore, the user does not have to supply a clock source to the device. the output data rate is 16.6 hz, which gives simultaneous 50 hz/60 hz rejection. the part operates with a single power supply from 2.5 v to 5.25 v. when operating from a 3 v supply, the power dissipation for the part is 225 w maximum. the ad7788/ad7789 is housed in a 10-lead msop.
ad7788/ad7789 rev. 0 | page 2 of 20 table of contents ad7789?specifications.................................................................. 3 ad7788?specifications.................................................................. 4 ad7788/ad7789 specifications..................................................... 5 timing characteristics..................................................................... 6 absolute maximum ratings............................................................ 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 10 on-chip registers .......................................................................... 11 communications register (rs1, rs0 = 0, 0) ......................................................................... 11 status register (rs1, rs0 = 0, 0; power-on/reset = 0x88 [ad7788] and 0x8c [ad7789]).................................................................. 12 mode register (rs1, rs0 = 0, 1; power-on/reset = 0x02)............................... 12 data register (rs1, rs0 = 1, 1; power-on/reset = 0x0000 [ad7788] and 0x000000 [ad7789]) .......................................................... 13 adc circuit information.............................................................. 14 overview ..................................................................................... 14 noise performance ..................................................................... 14 digital interface .......................................................................... 14 single conversion mode ....................................................... 15 continuous conversion mode............................................. 15 continuous read mode ........................................................ 16 circuit description......................................................................... 17 analog input channel ............................................................... 17 bipolar/unipolar configuration .............................................. 17 data output coding .................................................................. 17 reference input........................................................................... 17 v dd monitor ................................................................................ 18 grounding and layout .............................................................. 18 outline dimensions ....................................................................... 19 revision history revision 0: initial version
ad7788/ad7789 rev. 0 | page 3 of 20 ad7789?specifications 1 table 1. (v dd = 2.5 v to 5.25 v; refin(+) = 2.5 v; refin(C) = gnd; gnd = 0 v; all specifications t min to t max , unless otherwise noted.) parameter ad7789b nit test conditionscomments adc cannel specification output pdate rate 16.6 nom adc cannel no missing codes 2 24 bits min resolution 19 bits p-p output noise 1.5 v rms tp integral nonlinearit 15 ppm of fsr max offset error 3 v tp offset error drift s. temperature 10 nvc tp full-scale error 3 10 v tp gain drift s. temperature 0.5 ppmc tp power suppl reection 90 db min 100 db tp, ain = 1 v analog inpts differential input voltage ranges refin v nom refin = refin(+) C refin(C) absolute ain voltage limits 2 gnd C 30 mv v min v dd + 30 mv v max analog input current input cu rrent aries with input oltage. aerage input current 2 400 nav tp aerage input current drift 50 pavc tp normal mode reection 2 50 , 60 65 db min 50 1 , 60 1 common mode reection ain = 1 v dc 90 db min 100 db tp 50 , 60 2 100 db min 50 1 , 60 1 reference inpt refin voltage 2.5 v nom refin = refin(+) C refin(C) reference voltage range 2 0.1 v min v dd v max absolute refin voltage limits 2 gnd C 30 mv v min v dd + 30 mv v max aerage reference input current 0.5 av tp aerage reference input current drift 0.03 navc tp normal mode reection 2 50 , 60 65 db min 50 1 , 60 1 common mode reection ain = 1 v dc 110 db tp 50 , 60 110 db tp 50 1 , 60 1 1 temperature range C40c to +105c. 2 specification is not production tested, but is supported b characteriation data at initial product release. 3 full-scale error applies to both positie and negatie full scale and applies at the fact or calibration conditions (v dd = 4 v).
ad7788/ad7789 rev. 0 | page 4 of 20 ad7788?specifications 1 table 2. (v dd = 2.5 v to 5.25 v (b grade); v dd = 2.7 v to 5.25 v (a grade); refin(+) = 2.5 v; refin(C) = gnd; gnd = 0 v; all specifications t min to t max , unless otherwise noted.) parameter ad7788a, b nit test conditionscomments adc cannel specification output pdate rate 16.6 nom adc cannel no missing codes 2 16 bits min resolution 16 bits p-p output noise 1.5 v rms tp integral nonlinearit 15 ppm of fsr max b grade 50 ppm of fsr max a grade offset error 3 v tp offset error drift s. temperature 10 nvc tp full-scale error 3 10 v tp gain drift s. temperature 0.5 ppmc tp power suppl reection 90 db min b grade 90 db tp a grade analog inpts differential input voltage ranges refin v nom refin = refin(+) C refin(C) absolute ain voltage limits 2 gnd C 30 mv v min v dd + 30 mv v max analog input current input cu rrent aries with input oltage. aerage input current 2 400 nav tp aerage input current drift 50 pavc tp normal mode reection 2 50 , 60 65 db min b grade, 50 1 , 60 1 60 db min a grade, 50 1 , 60 1 common mode reection ain = 1 v dc 90 db min b grade, 100 db tp 90 db tp a grade 50 , 60 2 100 db min b grade, 50 1 , 60 1 100 db tp a grade, 50 1 , 60 1 reference inpt refin voltage 2.5 v nom refin = refin(+) C refin(C) reference voltage range 2 0.1 v min v dd v max absolute refin voltage limits 2 gnd C 30 mv v min v dd + 30 mv v max aerage reference input current 0.5 av tp aerage reference input current drift 0.03 navc tp normal mode reection 2 50 , 60 65 db min b grade, 50 1 , 60 1 60 db min a grade common mode reection ain = 1 v dc 100 db tp 50 , 60 110 db tp 50 1 , 60 1 1 temperature range b grade, C40c to +105c; a grade, C40c to +85c. 2 specification is not production tested but is supported b characteriation data at initial product release. 3 full-scale error applies to both positie and negatie full scale and applies at the fact or calibration conditions (v dd = 4 v).
ad7788/ad7789 rev. 0 | page 5 of 20 ad7788/ad7789 specifications table 3. parameter ad7788a, b ad7789b nit test conditionscomments logic inpts all inputs except scl 1 v inl , input low voltage 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v v in , input igh voltage 2.0 v min v dd = 3 v or 5 v scl onl (schmitt-triggered input) 1 v t (+) 1.42 v minv max v dd = 5 v v t (C) 0.81.4 v minv max v dd = 5 v v t (+) C v t (C) 0.30.85 v minv max v dd = 5 v v t (+) 0.92 v minv max v dd = 3 v v t (C) 0.41.1 v minv max v dd = 3 v v t (+) - v t (C) 0.30.85 v minv max v dd = 3 v input currents 1 a max v in = v dd input capacitance 10 pf tp all digital inputs logic otpts v o , output igh voltage 1 v dd C 0.6 v min v dd = 3 v, i sorce = 100 a v ol , output low voltage 1 0.4 v max v dd = 3 v, i sin = 100 a v o , output igh voltage 1 4 v min v dd = 5 v, i sorce = 200 a v ol , output low voltage 1 0.4 v max v dd = 5 v, i sin = 1.6 ma floating-state leaage current 1 a max floating-state output capa citance 10 pf tp data output coding offset binar poer reirements 2 power suppl voltage v dd C gnd 2.55.25 v minmax ad7789, ad7788b grade 2.75.25 v minmax ad7788a grade power suppl currents i dd current 75 a max 65 a tp, v dd = 3.6 v 80 a max 73 a tp, v dd = 5.25 v i dd (power-down mode) 1 a max 1 specification is not production tested but is supported b characteriation data at initial product release. 2 digital inputs eual to v dd or gnd.
ad7788/ad7789 rev. 0 | page 6 of 20 timing characteristics 1, 2 table 4. (v dd = 2.5 v to 5.25 v (ad7788b and ad7789), v dd = 2.7 v to 5.25 v (ad7788a); gnd = 0 v, refin(+) = 2.5 v, refin(C) = gnd, input logic 0 = 0 v, input logic 1 = v dd , unless otherwise noted.) parameter limit at t min , t max (b version) nit conditionscomments t 3 100 ns min scl igh pulsewidth t 4 100 ns min scl low pulsewidth read operation t 1 0 ns min cs falling edge to dotrd actie time 60 ns max v dd = 4.75 v to 5.25 v 80 ns max v dd = 2.7 v to 3.6 v t 2 3 0 ns min scl actie edge to data valid dela 4 60 ns max v dd = 4.75 v to 5.25 v 80 ns max v dd = 2.7 v to 3.6 v t 5 5, 6 10 ns min bus relinuish time after cs inactie edge 80 ns max t 6 100 ns max scl inactie edge to cs inactie edge t 7 10 ns min scl inactie edge to dotrd igh rite operation t 8 0 ns min cs falling edge to scl actie edge setup time 4 t 9 30 ns min data valid to scl edge setup time t 10 25 ns min data valid to scl edge old time t 11 0 ns min cs rising edge to scl edge old time 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10 to 90 of v dd ) and timed from a oltage leel of 1.6 v. 2 see figure 3 and figure 4. 3 these numbers are measured with the load circuit of figure 2 and defined as the time reuired for the output to cross the v ol or v o limits. 4 scl actie edge is falling edge of scl. 5 these numbers are deried from the measured time taen b the data output to change 0.5 v when loaded with the circuit of figu re 2. the measured number is then extrapolated bac to remoe the effects of charging or discharging the 50 pf capacitor. this means that the times uoted in the timing characteristics are the true bus relinuish times of the part and, as such, are independent of external bus loading capacitances. 6 rd returns high after a read of the adc. in single conersion mode and continuous conersion mode, the same data can be read agai n, if reuired, while rd is high, although care should be taen to ensure that subseuent reads do not occur close to the next output update. in continuous read mode, the digital word can be read onl once.
ad7788/ad7789 rev. 0 | page 7 of 20 03539-0-002 i sink (1.6ma with v dd = 5v, 100 p a with v dd = 3v) i source (200 p a with v dd = 5v, 100 p a with v dd = 3v) 1.6v to output pin 50pf figure 2. load circuit for timing characterization t 2 t 3 t 4 t 1 t 6 t 5 t 7 03539-0-003 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb figure 3. read cycle timing diagram 03539-0-004 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 figure 4. write cycle timing diagram
ad7788/ad7789 rev. 0 | page 8 of 20 absolute maximum ratings table 5. (t a = 25c, unless otherwise noted.) parameter rating v dd to gnd C0.3 v to +7 v analog input voltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v total ainrefin current (indefinite) 30 ma digital input voltage to gnd C0.3 v to v dd + 0.3 v digital output voltage to gnd C0.3 v to v dd + 0.3 v operating temperature range b grade C40c to +105c a grade C40c to +85c storage temperature range C65c to +150c maximum unction temperature 150c msop a thermal impedance
ad7788/ad7789 rev. 0 | page 9 of 20 pin configuration and fu nction descriptions 03539-0-005 ad7788/ ad7789 top view (not to scale) sclk 1 cs 2 ain(+) 3 ain(?) 4 ref(+) 5 din dout/rdy v dd gnd ref(?) 10 9 8 7 6 figure 5. pin configuration table 6. pin function descriptions pin no. mnemonic function 1 scl serial cloc input for data transfers to and from the adc. the scl has a schmitt- triggered input, maing the interface suitable for opto-isolated applications. the serial cloc can be continuous with all data transmitted in a continuous train of pulses. alternatiel, it can be a noncontinuous cloc with the information being trans- mitted to or from the adc in smaller batches of data. 2 cs chip select input. this is an actie low logic input used to select the adc. cs can be used to select the adc in sstems with more than one deice on the serial bus or as a frame snchroniation signal in communi- cating with the deice. cs can be hardwired low, allowing the adc to operate in 3-wire mode with scl, din, and dot used to interface with the deice. 3 ain(+) analog input. ain(+) is the positie terminal of the full differential analog input. 4 ain(C) analog input. ain(C) is the negatie termi- nal of the full differential analog input. 5 refin(+) positie reference input. refin(+) can lie anwhere between v dd and gnd + 0.1 v. the nominal reference oltage (refin(+) C refin(C)) is 2.5 v, but the part functions with a reference from 0.1 v to v dd . pin no. mnemonic function 6 refin(C) negatie reference input. this reference input can lie anwhere between gnd and v dd C 0.1 v. 7 gnd ground reference point. 8 v dd suppl voltage, 3 v or 5 v nominal. 9 dotrd serial data output data read output. dotrd seres a dual purpose. it functions as a serial data outp ut pin to access the out- put shift register of the adc. the output shift register can contain data from an of the on-chip data or control registers. in addition, dotrd operates as a data read pin, going low to indicate the completion of a conersion. if the data is not read after the conersion, the pin will go high before the next update occurs. the dotrd falling edge can be used as an interrupt to a processor, indicating that alid data is aailable. ith an external serial cloc, the data can be read using the dotrd pin. ith cs low, the datacontrol word informa- tion is placed on the dotrd pin on the scl falling edge and is alid on the scl rising edge. the end of a conersion is also indicated b the rd bit in the status register. hen cs is high, the dotrd pin is three-stated but the rd bit remains actie. 10 din serial data input to th e input shift register on the adc. data in this shift register is transferred to the control registers within the adc, the register selection bits of the communications register identifing the appropriate register.
ad7788/ad7789 rev. 0 | page 10 of 20 typical performance characteristics 03539-0-007 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 04080 20 60 100 120 140 db 160 0 frequency (hz) figure 6. frequency response with 16.6 hz update rate 03539-0-008 0 10 20 30 40 50 60 70 8388591 occurence 8388625 code v dd = 3v v ref = 2.048v t a = 25c rms noise = 1.25 p v figure 7. ad7789 noise histogram 03539-0-009 8 388591 0 200 400 600 800 code 1000 8 388625 read no. v dd = 3v, v ref = 2.048v, t a = 25c, rms noise = 1.25 p v figure 8. ad7789 noise plot 03539-0-013 0 0.5 1.0 1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 rms noise ( p v) 5.0 3.0 2.5 2.0 v ref (v) v dd = 5v update rate = 16.6hz t a = 25c figure 9. ad7788/ad7789 noise vs. v ref
ad7788/ad7789 rev. 0 | page 11 of 20 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described on the following pages. in the foll owing descriptions, set lesaocstatead cleared lesaocstatelessotersestated cnicainreierrr ecocatosrestersatrteolresterallcocatostoteartststarttarteoeratot oteco catosresteredatarttetotecocatosresterdetereseterteetoeratosareadorrte oerato adtocrestertsoeratotaeslaceforreadorrteoeratosocetesseetreadorrteoeratoto teselected resterscoleteteteraceretrstoereteectsarteoeratototecocatosresterssted ealtstateo teteraceadooerorateraresetteacstsdealtstateatorarteoeratototecoc atosres teristatosereteteraceseeceslostarteoeratooatleastseralcloccclestinret rsteacto tsdealtstateresettteetreartaleotlestetdesatosortecocatosrestercrtr ocrd catetetlocatocrdeottetsaretecocatosrestercrdeotestersttotedatastrea eer racetsdcatesteoeroresetdealtstatsotatt crcrcrcrcrcrcrcr en r r r crea c c table 7. communications register bit designations bit location bit name description cr7 en rite enable bit. a 0 must be written to this bit so that the write to the communications register actuall occurs. if a 1 is the first bit written, the part will not cl oc on to subseuent bits in the register. it will sta at this bit location until a 0 is written to this bit. once a 0 is written to the en bit, the next seen bits will be loaded to the communications register. cr6 0 this bit must be programmed with a logic 0 for correct operation. cr5Ccr4 rs1Crs0 register address bits. these address bits are used to select which of the adcs registers are being selected during this serial interface communication. see table 8. cr3 r a 0 in this bit location indicates that the next operati on will be a write to a specified register. a 1 in this position indicates that the next operation will be a read from the designated register. cr2 cread continuous read of the data registe r. hen this bit is set to 1 (and th e data register is selected), the serial interface is configured so th at the data register can be continuo usl read, i.e., the contents of the data register are placed on the dot pin automati call when the scl pulses are applied. the commu- nications register does not hae to be written to fo r data reads. to enable continuous read mode, the instruction 001111xx must be written to the communica tions register. to exit the continuous read mode, the instruction 001110xx must be written to the communications register while the rd pin is low. hile in continuous read mode , the adc monitors actiit on the di n line so that it can receie the instruction to exit continuous read mode. additionall, a reset will occur if 32 consecutie 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the deice. cr1Ccr0 c1Cc0 these bits are used to select the analog input channel. the differential channel can be selected (ain(+)ain(C)) or an internal short (ain(C)ain(C)) can be selected. alternatiel, the power suppl can be selected, i.e., the adc can measure the oltage on the power suppl, which is useful for monitoring power suppl ariation. the power su ppl oltage is diided b 5 and then applied to the modulator for conersion. the adc uses a 1.17 v 5 on-chip refe rence as the reference source for the analog to digital conersion. an change in channel resets the filter and a new conersion is started. table 8. register selection rs1 rs0 register register sie 0 0 communications register during a rite operation 8-bit 0 0 status register during a read operation 8-bit 0 1 mode register 8-bit 1 0 resered 8-bit 1 1 data register 16-bit (ad7788) 24-bit (ad7789) table 9. channel selection c1 c0 channel 0 0 ain(+) C ain(C) 0 1 resered 1 0 ain(C) C ain(C) 1 1 v dd monitor
ad7788/ad7789 rev. 0 | page 12 of 20 status register (rs1, rs0 = 0, 0; power- on/reset = 0x88 [ad7788] and 0x8c [ad7789]) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communication s register, select the next operation to be a read, and load bits rs1 and rs0 with 0. table 10 outlines the bit designations for the status register. sr0 through sr7 indicate the bit locations, sr denoting the bits are in the status register. sr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) 0(0) 0(0) 1(1) wl(1/0) ch1(0) ch0(0) table 10. status register bit designations bit location bit name description sr7 rd read bit for adc. cleared when data is written to th e adc data register. the rd bit is set automaticall after the adc data register has been read or a period of time before the data re gister is updated with a new conersion result to indicate to the user not to read the conersi on data. it is also set when the part is placed in powe-down mode. the end of a conersion is indicated b the dotrd pin also. this pin can be used as an alternatie to the status register for monitori ng the adc for conersion data. sr6 err adc error bit. this bit is written to at the same time as the rd bit. set to indicate that the result written to the adc data register has been clamped to al l 0s or all 1s. error sources include oerrange, underrange. cleared b a write operation to start a conersion. sr5 0 this bit is automaticall cleared . sr4 0 this bit is automaticall cleared . sr3 1 this bit is automaticall set . sr2 10 this bit is automaticall cleared if the deice is an ad 7788 and it is automaticall set if the deice is an ad7789. this bit can be used to dist inguish between the ad7788 and ad7789. sr1Csr0 c1Cc0 these bits indicate which channel is being conerted b the adc. mode register (rs1, rs0 = 0, 1; poer-onreset = 0x02) the mode register is an 8-bit register from which data can be read or to which data can be written. this register is used to co nfigure the adc for range, unipolar or bipolar mode, enable or disable the buffer, or place the deice into power-down mode. table 11 outli nes the bit designations for the mode register. mr0 through mr7 indicate the bit locations, mr denoting the bits are in the mode regist er. mr7 denotes the first bit of the data stream. the number in bracets indicates the power-onreset default status of that bit. an w rite to the setup register resets the modulator and filter and sets the rd bit. mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 md1(0) md0(0) 0(0) 0(0) 0(0) b (0) 1(1) 0(0) table 11. mode register bit designations bit location bit name description mr7Cmr6 md1Cmd0 mode select bits. these bits select between contin uous conersion mode, single conersion mode, and standb mode. in continuous coner sion mode, the adc continuousl performs conersions and places the result in the data register. rd goes low when a conersion is complete. the user can read these conersions b placing the deice in continuous re ad mode whereb the con ersions are automaticall placed on the dot line when scl pulses are applie d. alternatiel, the user can instruct the adc to output the conersion b writing to the communication s register. after power-on, the first conersion is aailable after a period 2 f adc while subseuent conersions are aailable at a freuenc of f adc . in single conersion mode, the adc is placed in power-down mode when conersions are not being performed. hen single conersion mode is selected, the adc powers up and performs a single conersion, which occurs after a period 2f adc . the conersion result in placed in the data register, rd goes low, and the adc returns to power-down mode. the conersi on remains in the data register and rd remains actie (low) until the data is read or another conersion is performed. see table 12.
ad7788/ad7789 rev. 0 | page 13 of 20 bit location bit name description mr5?mr3 0 this bit must be programme d with a logic 0 for correct operation. mr2 u/b unipolar/bipolar bit. set by user to enable unipolar coding, i.e., zero differential input will result in 000?000 output and a full-scale differentia l input will result in 111?111 output. cleared by the user to enable bipolar coding. negative full-scale differential input will result in an output code of 000?000, zero differential input will result in an output co de of 100?000, and a positive full-scale differential input will result in an output code of 111?111. mr1 1 this bit must be programmed with a logic 1 for correct operation. mr0 0 this bit must be programmed with a logic 0 for correct operation. table 12. operating modes md1 md0 mode 0 0 continuous conersion mode (default) 0 1 resered 1 0 single conersion mode 1 1 powerdown mode data register (rs1, rs0 = 1, 1; poer- onreset = 0x0000 ad7788 and 0x000000 ad7789) the conersion result from the adc is stored in this data register. this is a read-onl register. on completion of a read opera tion from this register, the rd bitpin is set.
ad7788/ad7789 rev. 0 | page 14 of 20 adc circuit information overview the ad7788/ad7789 is a low power adc that incorporates a - modulator and on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications. the part has one unbuffered differential input. the device requires an external reference voltage between 0.1 v and v dd . figure 10 shows the basic connections required to operate the part. 03539-0-006 in+ 10 p f 0.1 p f in? out? power supply out+ refin(+) cs dout/rdy sclk v dd gnd ain(+) ain(?) refin(?) ad7788/ ad7789 microcontroller figure 10. basic connection diagram the output rate of the ad7788/ad7789 (f adc ) is 16.6 hz with the settling time equal to 2 t adc (120.4 ms). normal mode rejection is the major function of the digital filter. simultaneous 50 hz and 60 hz rejection is optimized as notches are placed at both 50 hz and 60 hz with this update rate (see figure 6). noise performance the ad7788/ad7789 has an rms noise of 1.5 v rms typically, which corresponds to a peak-to-peak resolution of 16 bits for the ad7788 and 19 bits (equivalent to an effective resolution of 21.5 bits) for the ad7789. the numbers given are for the bipo- lar input range with a reference of 2.5 v. the noise was measured with a differential input voltage of 0 v. the peak-to- peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. the output noise comes from two sources. the first is the electrical noise in the semiconductor devices (device noise) used in the imple- mentation of the modulator. the second is quantization noise, which is added when the analog input is converted into the digital domain. digital interface as previously outlined, the ad7788/ad7789?s programmable functions are controlled using a set of on-chip registers. data is written to these registers via the part?s serial interface and read access to the on-chip registers is also provided by this interface. all communications with the part must start with a write to the communications register. after power-on or reset, the device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation and also determines to which register this read or write operation occurs. therefore, write access to any of the other registers on the part begins with a write operation to the communications register followed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register followed by a read operation from the selected register. the ad7788/ad7789?s serial interface consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on-chip registers while dout/ rdy is used for accessing from the on-chip registers. sclk is the serial clock input for the device and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin operates as a data ready signal also, the line going low when a new data-word is available in the output reg- ister. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the ad7788/ad7789 in systems where several compo- nents are connected to the serial bus. figure 3 and figure 4 show timing diagrams for interfacing to the ad7788/ad7789 with cs being used to decode the part. figure 3 shows the timing for a read operation from the ad7788/ad7789?s output shift register while figure 4 shows the timing for a write operation to the input shift register. in all modes except continuous read mode, it is possible to read the same word from the data register several times even though the dout/ rdy line returns high after the first read operation. however, care must be taken to ensure that the read operations have been completed before the next output update occurs. in continuous read mode, the data register can be read only once.
ad7788/ad7789 rev. 0 | page 15 of 20 the serial interface can operate in 3-wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7788/ad7789. the end of conversion can be monitored using the rdy bit in the status register. this scheme is suitable for interfacing to microcontrollers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idles high between data transfers. the ad7788/ad7789 can be operated with cs being used as a frame synchronization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs since cs would normally occur after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s on the din input. if a logic 1 is written to the ad7788/ad7789 line for at least 32 serial clock cycles, the serial interface is reset. this ensures that in 3-wire systems, the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. reset returns the interface to the state in which it is expecting a write to the communications register. this operation resets the contents of all registers to their power- on values. the ad7788/ad7789 can be configured to continuously con- vert or to perform a single conversion. see figure 11 through figure 13. single conversion mode n single onversion ode te is laed in sutdon ode eteen onversions en a single onver sion is initiated setting m to and m to in te ode register te oers u erors a single on version and ten returns to sutdon ode onversion ill reuire a tie eriod o t c r goes lo to indi ate te oletion o a onversion en te dataord as een read ro te data register r ill go ig cs is lo r ill reain ig until anoter onversion is initiated and oleted e data register an e read several ties i reuired even en r as gone ig continuous conversion mode is is te deault oeru ode e ill ontinuousl onvert te r in in te status register going lo ea tie a onversion is olete cs is lo te r line ill also go lo en a onversion is olete o read a onversion te user an rite to te ouniations register indiating tat te net oeration is a read o te data register e digital onversion ill e laed on te r in as soon as sc ulses are alied to te c r ill return ig en te onversion is read e user an read tis register additional ties i reuired oever te user ust ensure tat te data register is not eing aessed at te oletion o te net onversion or else te ne onversion ord ill e lost sc r cs igure single conversion
ad7788/ad7789 rev. 0 | page 16 of 20 continuous read mode rater tan rite to te ouniations register ea tie a onversion is olete to aess te data te an e laed in ontinuous read ode riting to te ouniations register te user needs onl to al te aroriate nuer o sc les to te c and te data ord ill autoatiall e laed on te r line en a onversion is olete en r goes lo to indiate te end o a onver sion suiient sc les ust e alied to te c and te data onversion ill e laed on te r line en te onversion is read r ill return ig until te net onversion is availale n tis ode te data an e read onl one lso te user ust ensure tat te dataord is read eore te net onversion is olete te user as not read te onversion eore te oletion o te net onversion or i insuiient serial los are alied to te to read te ord te serial outut register is reset en te net onversion is olete and te ne onversion is laed in te outut serial register o eit te ontinuous read ode te instrution ust e ritten to te ouniations register ile te r in is lo ile in te ontinuous read ode te c onitors ativit on te line so tat it an reeive te instrution to eit te ontinuous read ode dditionall a reset ill our i onseutive s are seen on ereore sould e eld lo in ontinuous read ode until an instrution is to e ritten to te devie sc r cs igure continuous conversion sc r cs c igure continuous read
ad7788/ad7789 rev. 0 | page 17 of 20 circuit description analog input channel the ad7788/ad7789 has one differential analog input channel that is connected to the modulator, i.e., the input is unbuffered. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the adc input. table 13 shows the allowable external resistance/capacitance values such that no gain error at the 16-bit level is introduced (ad7788), while table 14 shows the allowable external resis- tance/capacitance values such that no gain error at the 20-bit level is introduced (ad7789). table 13. external r-c combination for no 16-bit gain error (ad7788) c (pf) r () 50 22.8 100 13.1 500 3.3 1000 1.8 5000 360 table 14. external r-c combination for no 20-bit gain error (ad7789) c (pf) r () 50 16.7 100 9.6 500 2.2 1000 1.1 5000 160 the absolute input oltage includes the range between gnd C 30 mv and v dd + 30 mv. the negatie absolute input oltage limit does allow the possibilit of monitoring small true bipolar signals with respect to gnd. the absolute input oltage includes the range between gnd C 30 mv and v dd + 30 mv. the negatie absolute input oltage limit does allow the possibilit of monitoring small true bipolar signals with respect to gnd. bipolarnipolar configration the analog input to the ad7788ad7789 can accept either unipolar or bipolar input oltage ranges. a bipolar input range does not impl that the part can tolerate large negatie oltages with respect to sstem gnd. nipolar and bipolar signals on the ain(+) input are referenced to the oltage on the ain(C) input. for example, if ain(C) is 2.5 v and the adc is config- ured for unipolar mode, the input oltage range on the ain(+) pin is 2.5 v to 5 v. if the adc is configured for bipolar mode, the analog input range on the ain(+) input is 0 v to 5 v. the bipolarunipolar option is chosen b programming the b bit in the mode register. data otpt coding hen the adc is configured for unipolar operation, the output code is natural (straight) binar with a ero differential input oltage resulting in a code of 00...00, a midscale oltage result- ing in a code of 100...000, and a full-scale input oltage resulting in a code of 111...111. the output code for an analog input oltage can be represented as code n ain v ref eteacscoredorolaroeratoteott codesosetartaeatellscaleoltaereslt acodeoaeroderetaltoltaereslt acodeoadaostellscaletoltae resltacodeoeottcodeoraaalo toltaecaereresetedas code n ain v ref ere ain steaalotoltaead n orte aadortea referencein eaaasallderetaltcaaltor tecaelecoooderaeortesederetal tssrontov ereerecetsered adtereoreecessercsorceedaceslltrodce aerrorsereereceoltaerefinrefin refinsvoaltteaasc toaltreereceoltaesrovtov ialcatos ereteectatooltaeorcrretortetrasdcero teaalotalsodrestereereceoltaeorteart teeectoteloreecoseteectatosorce llereoedecasetealcatosratoetrcite aassedaoratoetrcalcatoalo osereerecesoldesed recoededvreereceoltaesorcesortea acldetearadarcareloose looerreerecesiteaalocrctrsesavoer sltereereceoltaesorcellreresoeead rooitscaseavreerecescastearor arcaesedaatesearelooerloose reerecesalsootetattereerecetsrodea edacedacloadecasetetedaceoeac reerecetsdacresstorcaactorcoatoso tesetscacasedcaerrorsdeedoteott edaceotesorcetatsdrtereerecets
ad7788/ad7789 rev. 0 | page 18 of 20 reference voltage sources like those recommended above (e.g., adr391) will typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on refin(+) without introducing gain errors in the system. deriving the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. external decoupling on the refin pins would not be recommended in this type of circuit configuration. v dd monitor along with converting external voltages, the analog input chan- nel can be used to monitor the voltage on the v dd pin. when the ch1 and ch0 bits in the communications register are set to 1, the voltage on the v dd pin is internally attenuated by 5 and the resultant voltage is applied to the - modulator using an inter- nal 1.17 v reference for analog to digital conversion. this is useful because variations in the power supply voltage can be monitored. grounding and layout since the analog inputs and reference inputs of the adc are differential, most of the voltages in the analog modulator are common-mode voltages. the excellent common-mode rejection of the part will remove common-mode noise on these inputs. the digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. the digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7788/ad7789 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the ad7788/ad7789 is so high, and the noise levels from the ad7788/ad7789 are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad7788/ad7789 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. a mini- mum etch technique is generally best for ground planes because it gives the best shielding. it is recommended that the ad 7788/ad7789?s gnd pin be tied to the agnd plane of the system. in any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destina- tions. avoid forcing digital currents to flow through the agnd sections of the layout. the ad7788/ad7789?s ground plane should be allowed to run under the ad7788/ad7789 to prevent noise coupling. the power supply lines to the ad7788/ad7789 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching sig- nals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid cross- over of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a micro- strip technique is by far the best, but it is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is important when using high resolution adcs. v dd should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. all logic chips should be decoupled with 0.1 f ceramic capacitors to dgnd.
ad7788/ad7789 rev. 0 | page 19 of 20 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba figure 14. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 15. ordering guide model temperature range pacage desc ription pacage option branding ad7788brm C40c to +105c 10-lead mini small outline pacage (msop) rm-10 cox AD7788BRM-REEL C40c to +105c 10-lead mini small outline pacage (msop) rm-10 cox ad7788arm C40c to +85c 10-lead mini small outline pacage (msop) rm-10 co ad7788arm-reel C40c to +85c 10-lead mini small outline pacage (msop) rm-10 co ad7789brm C40c to +105c 10-lead mini small outline pacage (msop) rm-10 co ad7789brm-reel C40c to +105c 10-lead mini small outline pacage (msop) rm-10 co
ad7788/ad7789 rev. 0 | page 20 of 20 notes ? 2003 analog devices, inc. all rights reserved. trademarks and regis- tered trademarks are the property of their respective companies. c03539-0-8/03(0)

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